今日のエラー

ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <get_data_mux0000> has no source
ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <r_write_or0000> has no source
ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <r_read_or0000> has no source
ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <get_data_and0000> has no source
ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_RDFIN> of logic node <get_data_or0000> has no source
ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <get_data_and0001> has no source
ERROR:Xst:1847 - Design checking failed

どこでエラーが出ているのか皆目見当がつかない。

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これに対するアンサー
http://www.stanford.edu/class/ee108b/labs/lab2_faq.htm

ERROR:Xst:1706 - Unit : port of logic node <_n0000> has no source
ERROR:Xst:1847 - Design checking failed

To get around this error, you will have to change the XST FSM (Finite State Machine) options. Do this, right-click on “Synthesis-XST” in the center left panel in Project Navigator. Select “Properties”. Once in the “Process Properties” menu, select the “HDL Options” tab. Then, click on the drop-menu of “FSM Encoding Algorithm”. Change the value from “Auto” to “None”. For some reason, XST is too smart in “Auto” mode and optimizes out the logic that drives the step_pulse signal.

英語読めない。無理死ぬ。

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Properties→Process Properties→HDL Options
で
FSM Encoding AlgorithmをNoneにしたけど、エラー。
さて、どうしませうか。

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バックアップ取ってたので差し替えたらコンパイル通った
意味不明
tortoiseSVNに何か原因があるかもしれない