ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <get_data_mux0000> has no source ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <r_write_or0000> has no source ERROR:Xst:1706 - Unit <LAB_DESIGN_SEQ>: port <sig_WRFIN> of logic node <r_read_or0000> has no …</r_read_or0000></sig_wrfin></lab_design_seq></r_write_or0000></sig_wrfin></lab_design_seq></get_data_mux0000></sig_wrfin></lab_design_seq>