反応が無い。

phy_init_doneが立たない。もうだめだ、あきらめるしかない。

2009-11-30

無理。

Error

ERROR:PhysDesignRules:368 - The signal is incomplete. The signal is not driven by any source pin in the design. ERROR:PhysDesignRules:10 - The network is completely unrouted. ERROR:Bitgen:25 - DRC detected 2 errors and 0 warnings. Please s…

2009-11-29

今日のエラー２

Error

ERROR:Xst:2035 - Port has illegal connections. This port is connected to an input buffer and other components.BANKが違うpinを繋ぐとなる。以後気をつけるように。

2009-11-28

今日のエラー１

Error ML501 verilog

今日のエラーって感じにシリーズ化しましょう。 ERROR:Xst:872 - "lab_design.v" line 325: Unsupported target. mig_32 ddr2_sdram( // SYSTEM .sys_rst_n (!PSWRST), .sys_clk_p (CLK333MP), .sys_clk_n (CLK333MN), .clk200_p (CLK200MP), .clk200_n (CLK…

2009-11-22

未知なるエラー

Error

ERROR:Place:864 - Incompatible IOB's are locked to the same bank 3 Conflicting IO Standards are: IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR List of locked IOB's: LED ERROR:Place:864 - …

2009-11-21

最初に気づけよ。

ML501

NET "DDR2_DQ[13]" LOC = "B22" ; #Bank 15 NET "DDR2_DQ[14]" LOC = "A22" ; #Bank 15 NET "DDR2_DQ[15]" LOC = "A23" ; #Bank 15 ... NET "sys_clk_p" LOC = "F14" ; #Bank 3 NET "sys_clk_n" LOC = "E13" ; #Bank 3 NET "clk200_p" LOC = "D13" ; #Bank 3…

2009-11-17

GNDに繋がってるってうるさい

Error

ERROR:Xst:2033 - Port I of Input buffer XLXI_2/u_mem_controller/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST is connected to GND ERROR:Xst:2033 - Port IB of Input buffer XLXI_2/u_mem_controller/u_ddr2_infrastructure/DIFF_ENDED_C…

2009-11-16

エラーは回避できないもの

Error

ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "CLK333MN" (Pad Signal = CLK333MN) SlaveBuffer symbol "mem_interface_top_infrastructure/lvds_sys_clk_input/SLAVEBUF.DIFFIN" (Output Signal = …

2009-11-15

結局エラーですね。わかります。

Error

死ねばいいのに。 ERROR:LIT:411 - IOBUFDS symbol "ddr2_sdram/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/gen_dqs_iob_ddr2.u_iobuf_dqs" (output signal=ddr2_sdram/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u…